{"id":186,"date":"2014-12-05T20:47:20","date_gmt":"2014-12-05T19:47:20","guid":{"rendered":"http:\/\/www.fabienm.eu\/flf\/?page_id=186"},"modified":"2021-06-01T14:14:49","modified_gmt":"2021-06-01T13:14:49","slug":"synthese","status":"publish","type":"page","link":"http:\/\/www.fabienm.eu\/flf\/logiciel\/synthese\/","title":{"rendered":"Synth\u00e8se"},"content":{"rendered":"<p>Les logiciels libres de synth\u00e8ses reste encore des projets de recherches soutenu par des laboratoires. Il est difficiles de s&rsquo;en servir en l&rsquo;\u00e9tat pour d\u00e9velopper sur des FPGA du commerce.<\/p>\n<ul>\n<li><a href=\"https:\/\/bitbucket.org\/alanmi\/abc\/src\">ABC<\/a>: Maintenu par l&rsquo;<a href=\"http:\/\/www.eecs.berkeley.edu\/~alanmi\/abc\/\">universit\u00e9 de Berkeley<\/a>, utilise un format de netlist AIGER et\/ou BLIF<\/li>\n<li><a href=\"_wp_link_placeholder\" data-wplink-edit=\"true\">OdinII<\/a><\/li>\n<\/ul>\n<p><strong>Verilog<\/strong><\/p>\n<ul>\n<li><a href=\"http:\/\/www.clifford.at\/yosys\/\">Yosys<\/a>: logiciel de synth\u00e8se verilog.<\/li>\n<li><a href=\"https:\/\/code.google.com\/p\/vtr-verilog-to-routing\/\">VTR<\/a>:\u00a0 Verilog To Routing, un projet universitaire d&rsquo;outils de synth\u00e8se et placement-routage utilisant une base verilog. VTR synth\u00e9tise \u00e0 destination de fpga th\u00e9orique, mais<a href=\"http:\/\/www.ece.ubc.ca\/~eddieh\/vtr-to-bitstream.html\"> il y aurait une m\u00e9thode pour cibler de vrais FPGA<\/a>.<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>Les logiciels libres de synth\u00e8ses reste encore des projets de recherches soutenu par des laboratoires. Il est difficiles de s&rsquo;en servir en l&rsquo;\u00e9tat pour d\u00e9velopper sur des FPGA du commerce. ABC: Maintenu par l&rsquo;universit\u00e9 de Berkeley, utilise un format de netlist AIGER et\/ou BLIF OdinII Verilog Yosys: logiciel de synth\u00e8se verilog. VTR:\u00a0 Verilog To Routing, &hellip; <a href=\"http:\/\/www.fabienm.eu\/flf\/logiciel\/synthese\/\" class=\"more-link\">Continuer la lecture de <span class=\"screen-reader-text\">Synth\u00e8se<\/span> <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":1011,"menu_order":8,"comment_status":"open","ping_status":"closed","template":"","meta":{"_uag_custom_page_level_css":"","footnotes":""},"class_list":["post-186","page","type-page","status-publish","hentry"],"uagb_featured_image_src":{"full":false,"thumbnail":false,"medium":false,"medium_large":false,"large":false,"1536x1536":false,"2048x2048":false,"post-thumbnail":false},"uagb_author_info":{"display_name":"Fabien Marteau","author_link":"http:\/\/www.fabienm.eu\/flf\/author\/admin\/"},"uagb_comment_info":1,"uagb_excerpt":"Les logiciels libres de synth\u00e8ses reste encore des projets de recherches soutenu par des laboratoires. Il est difficiles de s&rsquo;en servir en l&rsquo;\u00e9tat pour d\u00e9velopper sur des FPGA du commerce. ABC: Maintenu par l&rsquo;universit\u00e9 de Berkeley, utilise un format de netlist AIGER et\/ou BLIF OdinII Verilog Yosys: logiciel de synth\u00e8se verilog. VTR:\u00a0 Verilog To Routing,\u2026","_links":{"self":[{"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/pages\/186","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/comments?post=186"}],"version-history":[{"count":9,"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/pages\/186\/revisions"}],"predecessor-version":[{"id":1695,"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/pages\/186\/revisions\/1695"}],"up":[{"embeddable":true,"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/pages\/1011"}],"wp:attachment":[{"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/media?parent=186"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}