{"id":70,"date":"2014-11-16T13:50:57","date_gmt":"2014-11-16T12:50:57","guid":{"rendered":"http:\/\/www.fabienm.eu\/flf\/?page_id=70"},"modified":"2019-09-01T16:18:52","modified_gmt":"2019-09-01T15:18:52","slug":"placement-routage-bitstream","status":"publish","type":"page","link":"http:\/\/www.fabienm.eu\/flf\/logiciel\/placement-routage-bitstream\/","title":{"rendered":"Placement-routage, Bitstream"},"content":{"rendered":"<p>Il existe encore tr\u00e8s peux d&rsquo;outils permettant de g\u00e9n\u00e9rer les bitstream. Cependant on peut noter quelques projets qui avancent bien.<\/p>\n<p><strong>FPGA<\/strong><\/p>\n<ul>\n<li><a href=\"http:\/\/torc-isi.sourceforge.net\/\">Torc<\/a>: Permet de g\u00e9n\u00e9rer des bitstream pour Xilinx \u00e0 partir d&rsquo;une netlist en <a href=\"http:\/\/www.cs.indiana.edu\/hmg\/le\/project-home\/xilinx\/ise_5.2\/help\/data\/xdl\/xdl.html\">XDL<\/a>.<\/li>\n<li><a href=\"http:\/\/openpr-vt.sourceforge.net\/OpenPR\/OpenPR.html\">OpenPR<\/a>: Suite logiciel se basant sur Torc<\/li>\n<li><a href=\"http:\/\/rapidsmith.sourceforge.net\/\">RapidSmith<\/a>: \u00c9crit en Java, permet de g\u00e9n\u00e9rer des bitstream pour les fpga Xilinx Virtex 4 et 5.<\/li>\n<li><a href=\"https:\/\/code.google.com\/p\/debit\/\">debit<\/a>: Outil de reverse-ingeneering des bitstreams de Xilinx puis de Altera. Le projet semble \u00e0 l&rsquo;arret depuis 2010 \ud83d\ude41 Le site officiel <a href=\"http:\/\/www.ulogic.org\/\">u-logic<\/a> est down en permanence). Le projet maintenu par JB-Note est d\u00e9crit dans le papier suivant : <a href=\"http:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2014\/11\/Note2008.pdf\">\u00abFrom the bitstream to the netlist\u00bb.<\/a><\/li>\n<li><a href=\"https:\/\/github.com\/Wolfgang-Spraul\/fpgatools\/\">fpgatools<\/a>: cible seulement les <a href=\"http:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds160.pdf\">xc6slx9<\/a> de Xilinx pour le moment.<\/li>\n<li><a href=\"http:\/\/www.clifford.at\/icestorm\/\">icestorm<\/a>: Projet de reverse des bitstream ICE40 de lattice.\n<ul>\n<li><a href=\"https:\/\/github.com\/cseed\/arachne-pnr\">Arachne-pnr<\/a>:\u00a0 Placement-routage partant du format blif ciblant les ice40<\/li>\n<\/ul>\n<\/li>\n<li><a href=\"https:\/\/github.com\/azonenberg\/openfpga\/tree\/master\/src\/gp4par\">gp4par<\/a>\/<a href=\"https:\/\/github.com\/azonenberg\/openfpga\/\">openfpga<\/a>: cha\u00eene compl\u00e8te de d\u00e9veloppement ciblant les \u00abfpga\u00bb Greenpak4 (FPGA \u00abvirtuel\u00bb notamment contenu dans les PSoC de cypress).<\/li>\n<li><a href=\"https:\/\/github.com\/YosysHQ\/nextpnr\">nextpnr<\/a>\/<a href=\"https:\/\/symbiflow.github.io\/\">symbiflow<\/a>: La r\u00e9volution libre est en marche !<\/li>\n<\/ul>\n<p><strong>ASIC<\/strong><\/p>\n<ul>\n<li><a href=\"https:\/\/sourceforge.net\/projects\/alliancecad\/\">Alliance CAD<\/a>: permet de faire la simulation et\u00a0 le placement routage en VHDL mais cible les ASIC.<\/li>\n<li><a href=\"http:\/\/opencircuitdesign.com\/qflow\/\">Qflow<\/a>: Logiciel open-source permettant de d\u00e9velopper des ASIC \u00e0 partir de source en verilog.<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>Il existe encore tr\u00e8s peux d&rsquo;outils permettant de g\u00e9n\u00e9rer les bitstream. Cependant on peut noter quelques projets qui avancent bien. FPGA Torc: Permet de g\u00e9n\u00e9rer des bitstream pour Xilinx \u00e0 partir d&rsquo;une netlist en XDL. OpenPR: Suite logiciel se basant sur Torc RapidSmith: \u00c9crit en Java, permet de g\u00e9n\u00e9rer des bitstream pour les fpga Xilinx &hellip; <a href=\"http:\/\/www.fabienm.eu\/flf\/logiciel\/placement-routage-bitstream\/\" class=\"more-link\">Continuer la lecture de <span class=\"screen-reader-text\">Placement-routage, Bitstream<\/span> <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":1011,"menu_order":5,"comment_status":"open","ping_status":"closed","template":"","meta":{"_uag_custom_page_level_css":"","footnotes":""},"class_list":["post-70","page","type-page","status-publish","hentry"],"uagb_featured_image_src":{"full":false,"thumbnail":false,"medium":false,"medium_large":false,"large":false,"1536x1536":false,"2048x2048":false,"post-thumbnail":false},"uagb_author_info":{"display_name":"Fabien Marteau","author_link":"http:\/\/www.fabienm.eu\/flf\/author\/admin\/"},"uagb_comment_info":1,"uagb_excerpt":"Il existe encore tr\u00e8s peux d&rsquo;outils permettant de g\u00e9n\u00e9rer les bitstream. Cependant on peut noter quelques projets qui avancent bien. FPGA Torc: Permet de g\u00e9n\u00e9rer des bitstream pour Xilinx \u00e0 partir d&rsquo;une netlist en XDL. OpenPR: Suite logiciel se basant sur Torc RapidSmith: \u00c9crit en Java, permet de g\u00e9n\u00e9rer des bitstream pour les fpga Xilinx\u2026","_links":{"self":[{"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/pages\/70","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/comments?post=70"}],"version-history":[{"count":15,"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/pages\/70\/revisions"}],"predecessor-version":[{"id":962,"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/pages\/70\/revisions\/962"}],"up":[{"embeddable":true,"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/pages\/1011"}],"wp:attachment":[{"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/media?parent=70"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}