{"id":1147,"date":"2019-11-05T13:44:22","date_gmt":"2019-11-05T12:44:22","guid":{"rendered":"http:\/\/www.fabienm.eu\/flf\/?p=1147"},"modified":"2021-09-16T09:05:34","modified_gmt":"2021-09-16T08:05:34","slug":"chisel-tips","status":"publish","type":"post","link":"http:\/\/www.fabienm.eu\/flf\/chisel-tips\/","title":{"rendered":"Chisel Tips"},"content":{"rendered":"\n

This page lists some tips for Chisel that I could glean here and there.<\/p>\n\n\n\t\t\t\t

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\n\t\t\t\t\t\t\tTable Of Contents\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t
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  1. Bidirectional signal<\/a>
  2. dontTouch : keep register names in verilog<\/a>
  3. DontCare output signals<\/a>
  4. Keep signal and variables names in Verilog<\/a>
  5. UInt() to Vec()<\/a>
  6. Split an UInt() in a Vec() of \u00absub\u00bb UInt()<\/a>
  7. Initialize Vec() of Reg()<\/a>
  8. Concatenate value in one UInt()<\/a>
  9. Initialize Bundle<\/a>
  10. Test some chisel code in live<\/a>
  11. For more Chisel Cookbook<\/a><\/ol>\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\n\n\n

    Bidirectional signal<\/h4>\n\n\n\n

    Bidirectionnal signals are not possible inside an FPGA or an ASIC. But it can be usefull on the boundary to drive signal like tristate buffer.<\/p>\n\n\n\n

    To use Bidirectionnal signal use Analog<\/a>() in conjonction with RawModule or BlackBox :<\/p>\n\n\n\n

    class TopDesign extends RawModule {\n  val tristatebuf = Analog(1.W)\n...\n}<\/code><\/pre>\n\n\n\n
    Connexion is made with bulk connector ‘<>’ :<\/p>\n\n\n\n
    tristatebuf <> myblackbox.io.tristate<\/code><\/pre>\n\n\n\n
    dontTouch : keep register names in verilog<\/h4>\n\n\n\n
    Tip from stackoverflow<\/a>.<\/p>\n\n\n\n
    Sometimes, we have to keep register in verilog emitted code. But Chisel obtimize it and it often disapear. To keep it, use dontTouch() :<\/p>\n\n\n\n
      val version = dontTouch(RegInit(1.U(8.W)))<\/code><\/pre>\n\n\n\n
    Get following in verilog module:<\/p>\n\n\n\n
      reg [7:0] version; \/\/ @[wbgpio.scala 20:34]\n...\n    if (reset) begin\n      version <= 8'h1;\n    end<\/code><\/pre>\n\n\n\n
    DontCare output signals<\/h4>\n\n\n\n
    All module output must be defined to avoid this kind of warning :<\/p>\n\n\n\n
    [error] (run-main-0) firrtl.passes.CheckInitialization$RefNotInitializedException:  : [module ChisNesPad]  Reference io is not fully initialized.\n[error]    : io.data.valid <= VOID\n[error] firrtl.passes.CheckInitialization$RefNotInitializedException:  : [module ChisNesPad]  Reference io is not fully initialized.\n[error]    : io.data.valid <= VOID\n[error] Nonzero exit code: 1\n[error] (Compile \/ runMain) Nonzero exit code: 1\n[error] Total time: 12 s, completed 10 d\u00e9c. 2019 13:25:11<\/code><\/pre>\n\n\n\n
    But at the begining of a design, we don’t know what to write. To avoid this error we can use DontCare<\/code> object :<\/p>\n\n\n\n
      io.data.valid := DontCare<\/code><\/pre>\n\n\n\n
    Keep signal and variables names in Verilog<\/h4>\n\n\n\n
    See the good response from Jack Koening on stackoverflow<\/a>.<\/p>\n\n\n\n
    UInt() to Vec()<\/strong><\/h4>\n\n\n\n
    An UInt() can be converted to a Vec of Bool() with asBools<\/a>:<\/p>\n\n\n\n
    val foo = Vec(5, Bool())\nval bar = UInt(5.W)\n\nfoo := bar.asBools\nInitialize Vec() of Reg()<\/code><\/pre>\n\n\n\n
    Split an UInt() in a Vec() of \u00absub\u00bb UInt()<\/h4>\n\n\n\n
    Question asked on stackoverflow<\/a>.<\/p>\n\n\n\n
    If we have a 16 bits register declared like that.<\/p>\n\n\n\n
    val counterReg = RegInit(0.U(16.W))<\/code><\/pre>\n\n\n\n
    And we want to do indexed dibit assignment on module output like that :<\/p>\n\n\n\n
    \/\/..\n  val io = IO(new Bundle {\n     val dibit = Output(UInt(2.W))\n  })\n\/\/..\nvar indexReg = RegInit(0.U(4.W))\n\/\/..\nio.dibit = vectorizedCounter(indexReg) \/\/xxx doesn't work<\/code><\/pre>\n\n\n\n
    We could do it like that:<\/p>\n\n\n\n
    io.dibit := (counterReg >> indexReg)(1, 0)<\/code><\/pre>\n\n\n\n
    Initialize Vec() of Reg()<\/h4>\n\n\n\n
     val initRegOfVec = RegInit(VecInit(Seq.fill(4)(0.U(32.W))))<\/code><\/pre>\n\n\n\n
    Concatenate value in one UInt()<\/h4>\n\n\n\n
    Of course we can use Cat(), but it take only 2 parameters. With ‘##’ we can chain more signals:<\/p>\n\n\n\n
    val a = Reg(UInt(1.W))\nval b = Reg(UInt(1.W))\nval c = Reg(UInt(1.W))\nval y = Reg(UInt(3.W))\n\ny := a ## b ## c<\/code><\/pre>\n\n\n\n
    With a Vec() declared like it :<\/p>\n\n\n\n
    val outputReg = RegInit(0.U((dibitCount*2).W)\nval valueVecReg = RegInit(VecInit(Seq.fill(dibitCount)(0.U(2.W))))\n\nouptutReg := valueVecReg.reduce(_ ## _)<\/code><\/pre>\n\n\n\n
    Initialize Bundle<\/h4>\n\n\n\n
    Question asked on stackoverflow<\/a>. Same question on stackoverflow but with ‘1’ initialization.<\/a><\/p>\n\n\n\n
    If we have a Bundle declared like that :<\/p>\n\n\n\n
    class RValue (val cSize: Int = 16) extends Bundle {\n  val rvalue = Output(UInt(cSize.W))\n  val er     = Output(UInt((cSize\/2).W))\n  val part   = Output(Bool()) \/* set if value is partial *\/\n}<\/code><\/pre>\n\n\n\n
    And we want to make a register with initialized value we can use the new interface<\/a> named BundleLiterals:<\/p>\n\n\n\n
    import chisel3.experimental.BundleLiterals._\n...\nval valueReg = RegInit((new RValue(cSize)).Lit(\n          _.rvalue -> 1.U,\n          _.er -> 2.U,\n          _.part -> true.B)<\/code><\/pre>\n\n\n\n
    Or if we just want to initialize to all 0 values we can do that<\/a> :<\/p>\n\n\n\n
    val valueReg = RegInit(0.U.asTypeOf(new RValue(cSize))<\/code><\/pre>\n\n\n\n
    Test some chisel code in live<\/h4>\n\n\n\n
    Question asked on stackoverflow<\/a>.<\/p>\n\n\n\n
    It can be usefull to be able to test code in console before launching the big compilation. It’s possible in directory where your project build.sbt is :<\/p>\n\n\n\n
    $ cd myproject\/\n$ sbt\nsbt:myproject> console\nscala><\/code><\/pre>\n\n\n\n
    And once in the scala console chisel import can be done :<\/p>\n\n\n\n
    scala> import chisel3._\nimport chisel3._\nscala> val plop = \"b0010101010001\".U(13.W)\nplop: chisel3.UInt = UInt<13>(1361)\n<\/code><\/pre>\n\n\n\n
    Type Ctrl+D to quit.<\/p>\n\n\n\n
    For more simplicity it’s also possible to use the Scaties website<\/a> in live.<\/p>\n\n\n\n
    For more Chisel Cookbook<\/h4>\n\n\n\n
    See :<\/p>\n\n\n\n