Les constructeurs de FPGA fournissent des mod\u00e8les VHDL de leurs primitives. Chez Xilinx cela se pr\u00e9sente sous la forme d’une librairie nomm\u00e9e UNISIM.<\/p>\n\n\n\n
Le logiciel libre de simulation GHDL<\/a> n\u2019inclut pas les sources VHDL de cette librairie dans son d\u00e9p\u00f4t officiel car \u00e7a n’est pas sa propri\u00e9t\u00e9. Cependant, GHDL fourni des scripts<\/a> permettant de les pr\u00e9-compiler pour son projet.<\/p>\n\n\n\n Nous allons voir ici comment se servir des primitives disponible dans vivado avec une simulation utilisant CocoTB<\/a>.<\/p>\n\n\n\n Les sources des primitives se trouvent dans le r\u00e9pertoire d’installation de Vivado<\/a><\/p>\n\n\n\n Pour les retrouver on peut utiliser la commande fd-find<\/a> comme ceci :<\/p>\n\n\n\n On s’assure d’avoir la variable d’environnement XILINX_VIVADO bien configur\u00e9e :<\/p>\n\n\n\n Il peut \u00eatre int\u00e9ressant de mettre les librairies compil\u00e9 \u00e0 cet endroit pour y faire r\u00e9f\u00e9rence depuis tous ses projets ensuite :<\/p>\n\n\n\n Pour compiler la librairie unisim pour vivado on utilisera le script suivant :<\/p>\n\n\n\n La compilation prend un temps infini<\/strong>, compter au moins 5 minutes sur un PC muni de 16 c\u0153urs. Il suffira ensuite d’ajouter les lignes suivantes \u00e0 son makefile CocoTB :<\/p>\n\n\n\n Et roulez jeunesse.<\/p>\n","protected":false},"excerpt":{"rendered":" Les constructeurs de FPGA fournissent des mod\u00e8les VHDL de leurs primitives. Chez Xilinx cela se pr\u00e9sente sous la forme d’une librairie nomm\u00e9e UNISIM. Le logiciel libre de simulation GHDL n\u2019inclut pas les sources VHDL de cette librairie dans son d\u00e9p\u00f4t officiel car \u00e7a n’est pas sa propri\u00e9t\u00e9. Cependant, GHDL fourni des scripts permettant de les … Continuer la lecture de Utiliser UNISIM avec GHDL et CocoTB<\/span> data\/vhdl\/src\/unisims\/<\/code><\/pre>\n\n\n\n$ fd unisim -e vhd\nVitis\/2021.2\/scripts\/rt\/data\/unisim_VCOMP.vhd\nVitis\/2021.2\/scripts\/rt\/data\/unisim_VCOMP_8h.vhd\nVitis\/2021.2\/scripts\/rt\/data\/unisim_VCOMP_diablo.vhd\nVitis\/2021.2\/scripts\/rt\/data\/unisim_VCOMP_e.vhd\nVitis\/2021.2\/scripts\/rt\/data\/unisim_VPKG.vhd\nVivado\/2021.2\/data\/vhdl\/src\/unisims\/unisim_VCOMP.vhd\nVivado\/2021.2\/data\/vhdl\/src\/unisims\/unisim_VPKG.vhd\nVivado\/2021.2\/data\/vhdl\/src\/unisims\/unisim_retarget_VCOMP.vhd\nVivado\/2021.2\/ids_lite\/ISE\/vhdl\/src\/unisims\/unisim_VCOMP.vhd\nVivado\/2021.2\/ids_lite\/ISE\/vhdl\/src\/unisims\/unisim_VPKG.vhd\nVivado\/2021.2\/scripts\/rt\/data\/unisim_VCOMP.vhd\nVivado\/2021.2\/scripts\/rt\/data\/unisim_VCOMP_8h.vhd\nVivado\/2021.2\/scripts\/rt\/data\/unisim_VCOMP_diablo.vhd\nVivado\/2021.2\/scripts\/rt\/data\/unisim_VCOMP_e.vhd\n\n# et pour unimacro :\n$ fd unimacro -e vhd\nVitis\/2021.2\/scripts\/rt\/data\/unimacro_VCOMP.vhd\nVivado\/2021.2\/data\/vhdl\/src\/unimacro\/unimacro_VCOMP.vhd\nVivado\/2021.2\/ids_lite\/ISE\/vhdl\/src\/unimacro\/unimacro_VCOMP.vhd\nVivado\/2021.2\/scripts\/rt\/data\/unimacro_VCOMP.vhd$ fd unimacro -e vhd\nVitis\/2021.2\/scripts\/rt\/data\/unimacro_VCOMP.vhd\nVivado\/2021.2\/data\/vhdl\/src\/unimacro\/unimacro_VCOMP.vhd\nVivado\/2021.2\/ids_lite\/ISE\/vhdl\/src\/unimacro\/unimacro_VCOMP.vhd\nVivado\/2021.2\/scripts\/rt\/data\/unimacro_VCOMP.vhd\n$ fd unimacro -e vhd\nVitis\/2021.2\/scripts\/rt\/data\/unimacro_VCOMP.vhd\nVivado\/2021.2\/data\/vhdl\/src\/unimacro\/unimacro_VCOMP.vhd\nVivado\/2021.2\/ids_lite\/ISE\/vhdl\/src\/unimacro\/unimacro_VCOMP.vhd\nVivado\/2021.2\/scripts\/rt\/data\/unimacro_VCOMP.vhd\n<\/code><\/pre>\n\n\n\n$ export XILINX_VIVADO=\/opt\/Xilinx\/Vivado\/2021.2\/Vivado\/2021.2\/\n$ echo $XILINX_VIVADO\n\/opt\/Xilinx\/Vivado\/2021.2\/Vivado\/2021.2\/<\/code><\/pre>\n\n\n\ncd data\/vhdl\nmkdir ghdl\ncd ghdl\n\/usr\/local\/lib\/ghdl\/vendors\/compile-xilinx-vivado.sh -all --vhdl2008\n[...]\n<\/code><\/pre>\n\n\n\n\/usr\/local\/lib\/ghdl\/vendors\/compile-xilinx-vivado.sh -a --vhdl2008\nLoading environment...\nNot all Xilinx primitives are VHDL-2008 compatible! Setting CONTINUE_ON_ERROR to TRUE.\nAnalyzing library 'unisim'...\nCreating VHDL Library 'unisim'...\nAnalyzing files into library 'unisim'...\n WARNING: \/opt\/Xilinx\/Vivado\/2020.2\/data\/vhdl\/src\/unisims\/primitive\/SYSMONE4.vhd:1536:44:warning: prefix of array attribute must be an object name [-Wattribute]\nSCRIPT ERROR: Unfiltered line\nv_str_time_length := time'image(now)'length;\nSCRIPT ERROR: Unfiltered line\n^\n Warnings detected by filtering script.\nAnalyzing library 'secureip'...\nCreating VHDL Library 'secureip'...\nAnalyzing files into library 'secureip'...\nAnalyzing library 'unimacro'...\nCreating VHDL Library 'unimacro'...\nAnalyzing files into library 'unimacro'...\nAnalyzing library 'unifast'...\nCreating VHDL Library 'unifast'...\nAnalyzing files into library 'unifast'...\nAnalyzing library 'secureip'...\nCreating VHDL Library 'secureip'...\nAnalyzing files into library 'secureip'...\n WARNING: \/opt\/Xilinx\/Vivado\/2020.2\/data\/vhdl\/src\/unifast\/secureip\/GTHE2_CHANNEL.vhd:29:1:warning: entity \"gthe2_channel\" was also defined in file \"\/opt\/Xilinx\/Vivado\/2020.2\/data\/vhdl\/src\/unisims\/secureip\/GTHE2_CHANNEL.vhd\" [-Wlibrary]\nSCRIPT ERROR: Unfiltered line\nlibrary IEEE;\nSCRIPT ERROR: Unfiltered line\n^\n Warnings detected by filtering script.\n WARNING: \/opt\/Xilinx\/Vivado\/2020.2\/data\/vhdl\/src\/unifast\/secureip\/GTXE2_CHANNEL.vhd:34:1:warning: entity \"gtxe2_channel\" was also defined in file \"\/opt\/Xilinx\/Vivado\/2020.2\/data\/vhdl\/src\/unisims\/secureip\/GTXE2_CHANNEL.vhd\" [-Wlibrary]\nSCRIPT ERROR: Unfiltered line\nlibrary IEEE;\nSCRIPT ERROR: Unfiltered line\n^\n Warnings detected by filtering script.\n--------------------------------------------------------------------------------\nCompiling Xilinx Vivado libraries [SUCCESSFUL]\n<\/code><\/pre>\n\n\n\n\nEXTRA_ARGS+=--std=08\nEXTRA_ARGS+=-frelaxed-rules\n\nUNISIMDIR=$(VIVADODIR)\/data\/vhdl\/ghdl\/xilinx-vivado\/unisim\/v93\nEXTRA_ARGS=-P$(UNISIMDIR)\n...\nEXTRA_ARGS=-P$(UNIMACRODIR)<\/code><\/pre>\n\n\n\n