{"id":787,"date":"2018-09-24T12:11:46","date_gmt":"2018-09-24T11:11:46","guid":{"rendered":"http:\/\/www.fabienm.eu\/flf\/?p=787"},"modified":"2018-09-24T12:11:46","modified_gmt":"2018-09-24T11:11:46","slug":"verilator-4-002","status":"publish","type":"post","link":"http:\/\/www.fabienm.eu\/flf\/verilator-4-002\/","title":{"rendered":"Verilator 4.002"},"content":{"rendered":"<p>La version\u00a04.002 de Verilator <a href=\"https:\/\/www.veripool.org\/papers\/Verilator_v4_Multithreaded_OrConf2018.pdf\">a\u00a0\u00e9t\u00e9\u00a0annonc\u00e9e<\/a> \u00e0 la conf\u00e9rence <a href=\"https:\/\/orconf.org\/\">ORConf2018<\/a> en\u00a0Pologne.<\/p>\n<p>Verilator est sans conteste le simulateur <a href=\"https:\/\/en.wikipedia.org\/wiki\/Hardware_description_language\">HDL<\/a> <em>open\u00a0source<\/em> le plus rapide du \u00ab\u00a0march\u00e9\u00a0\u00bb. Il permet de simuler des <a href=\"http:\/\/www.fabienm.eu\/flf\/et-pourquoi-pas-portegramme\/\">porte\u2010grammes<\/a> \u00e9crits en Verilog <strong>synth\u00e9tisable<\/strong>.<\/p>\n<p><img decoding=\"async\" title=\"Source : https:\/\/www.veripool.org\/img\/verilator_256_200_min.png\" src=\"https:\/\/img.linuxfr.org\/img\/68747470733a2f2f7777772e76657269706f6f6c2e6f72672f696d672f766572696c61746f725f3235365f3230305f6d696e2e706e67\/verilator_256_200_min.png\" alt=\"Le nouveau logo de Verilator\" \/><\/p>\n<ul class=\"links\">\n<li id=\"link_102672\" class=\"link\" lang=\"en\" data-url=\"\/redaction\/links\/102672\/modifier\"><a class=\"hit_counter\" title=\"https:\/\/www.veripool.org\/wiki\/verilator\" href=\"https:\/\/linuxfr.org\/redirect\/102672\" hreflang=\"en\" data-hit=\"102672\">Page officielle de Verilator<\/a> (182 clics)<\/li>\n<li id=\"link_102673\" class=\"link\" lang=\"fr\" data-url=\"\/redaction\/links\/102673\/modifier\"><a class=\"hit_counter\" title=\"http:\/\/www.fabienm.eu\/flf\/icarus-vs-verilator\/\" href=\"https:\/\/linuxfr.org\/redirect\/102673\" hreflang=\"fr\" data-hit=\"102673\">Comparaison de temps de simulation Verilator vs Icarus<\/a> (59 clics)<\/li>\n<li id=\"link_102698\" class=\"link\" lang=\"en\" data-url=\"\/redaction\/links\/102698\/modifier\"><a class=\"hit_counter\" title=\"https:\/\/www.veripool.org\/news\/241-Verilator-Verilator-4-002-Released\" href=\"https:\/\/linuxfr.org\/redirect\/102698\" hreflang=\"en\" data-hit=\"102698\">Notes de version de la\u00a04.002<\/a> (21 clics)<\/li>\n<li id=\"link_102738\" class=\"link\" lang=\"en\" data-url=\"\/redaction\/links\/102738\/modifier\"><a class=\"hit_counter\" title=\"https:\/\/www.veripool.org\/papers\/Verilator_v4_Multithreaded_OrConf2018.pdf\" href=\"https:\/\/linuxfr.org\/redirect\/102738\" hreflang=\"en\" data-hit=\"102738\">La pr\u00e9sentation \u00e0 ORConf2018<\/a> (25 clics)<\/li>\n<\/ul>\n<p><a href=\"https:\/\/linuxfr.org\/news\/verilator-4-002\">La suite sur la d\u00e9p\u00eache linuxfr<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>La version\u00a04.002 de Verilator a\u00a0\u00e9t\u00e9\u00a0annonc\u00e9e \u00e0 la conf\u00e9rence ORConf2018 en\u00a0Pologne. Verilator est sans conteste le simulateur HDL open\u00a0source le plus rapide du \u00ab\u00a0march\u00e9\u00a0\u00bb. Il permet de simuler des porte\u2010grammes \u00e9crits en Verilog synth\u00e9tisable. Page officielle de Verilator (182 clics) Comparaison de temps de simulation Verilator vs Icarus (59 clics) Notes de version de la\u00a04.002 (21 &hellip; <a href=\"http:\/\/www.fabienm.eu\/flf\/verilator-4-002\/\" class=\"more-link\">Continuer la lecture de <span class=\"screen-reader-text\">Verilator 4.002<\/span> <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_uag_custom_page_level_css":"","footnotes":""},"categories":[3,27,20],"tags":[29,30],"class_list":["post-787","post","type-post","status-publish","format-standard","hentry","category-langages","category-verilator","category-verilog","tag-verilator","tag-verilog"],"uagb_featured_image_src":{"full":false,"thumbnail":false,"medium":false,"medium_large":false,"large":false,"1536x1536":false,"2048x2048":false,"post-thumbnail":false},"uagb_author_info":{"display_name":"Fabien Marteau","author_link":"http:\/\/www.fabienm.eu\/flf\/author\/admin\/"},"uagb_comment_info":1,"uagb_excerpt":"La version\u00a04.002 de Verilator a\u00a0\u00e9t\u00e9\u00a0annonc\u00e9e \u00e0 la conf\u00e9rence ORConf2018 en\u00a0Pologne. Verilator est sans conteste le simulateur HDL open\u00a0source le plus rapide du \u00ab\u00a0march\u00e9\u00a0\u00bb. Il permet de simuler des porte\u2010grammes \u00e9crits en Verilog synth\u00e9tisable. Page officielle de Verilator (182 clics) Comparaison de temps de simulation Verilator vs Icarus (59 clics) Notes de version de la\u00a04.002 (21\u2026","_links":{"self":[{"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/posts\/787","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/comments?post=787"}],"version-history":[{"count":1,"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/posts\/787\/revisions"}],"predecessor-version":[{"id":788,"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/posts\/787\/revisions\/788"}],"wp:attachment":[{"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/media?parent=787"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/categories?post=787"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/tags?post=787"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}