{"id":1246,"date":"2019-12-09T15:15:01","date_gmt":"2019-12-09T14:15:01","guid":{"rendered":"http:\/\/www.fabienm.eu\/flf\/?p=1246"},"modified":"2019-12-09T15:42:00","modified_gmt":"2019-12-09T14:42:00","slug":"verilog-simulation-flags","status":"publish","type":"post","link":"https:\/\/www.fabienm.eu\/flf\/verilog-simulation-flags\/","title":{"rendered":"Verilog simulation Flags"},"content":{"rendered":"\n<p>Apparently, there is no Verilog standard to say \u00abhey we are on simulation here\u00bb. Each software have it&rsquo;s own flag for that.<\/p>\n\n\n\n<p><strong>Xilinx iSim<\/strong><\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>`ifdef XILINX_ISIM\n  \/\/ code for simulation with isim\n`else\n  \/\/ code for synthesis\n`endif<\/code><\/pre>\n\n\n\n<p><strong>Mentor Modelsim<\/strong><\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>`ifdef MODEL_TECH\n  \/\/ code for simulation with modelsim\n`else\n  \/\/ code for synthesis\n`endif<\/code><\/pre>\n\n\n\n<p><strong>Icarus Verilog<\/strong><\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>?<\/code><\/pre>\n\n\n\n<p><strong>Cocotb<\/strong><\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>`ifdef COCOTB_SIM\n  \/\/ code for simulation with cocotb (should be cumulated with other simulator I think)\n`else\n  \/\/ code for synthesis\n`endif<\/code><\/pre>\n","protected":false},"excerpt":{"rendered":"<p>Apparently, there is no Verilog standard to say \u00abhey we are on simulation here\u00bb. Each software have it&rsquo;s own flag for that. Xilinx iSim Mentor Modelsim Icarus Verilog Cocotb<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_uag_custom_page_level_css":"","footnotes":""},"categories":[3,20],"tags":[117,159],"class_list":["post-1246","post","type-post","status-publish","format-standard","hentry","category-langages","category-verilog","tag-tip","tag-tricks"],"uagb_featured_image_src":{"full":false,"thumbnail":false,"medium":false,"medium_large":false,"large":false,"1536x1536":false,"2048x2048":false,"post-thumbnail":false},"uagb_author_info":{"display_name":"Fabien Marteau","author_link":"https:\/\/www.fabienm.eu\/flf\/author\/admin\/"},"uagb_comment_info":0,"uagb_excerpt":"Apparently, there is no Verilog standard to say \u00abhey we are on simulation here\u00bb. Each software have it&rsquo;s own flag for that. Xilinx iSim Mentor Modelsim Icarus Verilog Cocotb","_links":{"self":[{"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/posts\/1246","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/comments?post=1246"}],"version-history":[{"count":3,"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/posts\/1246\/revisions"}],"predecessor-version":[{"id":1249,"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/posts\/1246\/revisions\/1249"}],"wp:attachment":[{"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/media?parent=1246"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/categories?post=1246"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/tags?post=1246"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}