{"id":2426,"date":"2025-01-17T22:10:35","date_gmt":"2025-01-17T21:10:35","guid":{"rendered":"https:\/\/www.fabienm.eu\/flf\/?p=2426"},"modified":"2025-01-19T07:39:49","modified_gmt":"2025-01-19T06:39:49","slug":"prise-en-main-de-la-gatematea1-evb","status":"publish","type":"post","link":"https:\/\/www.fabienm.eu\/flf\/prise-en-main-de-la-gatematea1-evb\/","title":{"rendered":"Prise en main de la GateMateA1-EVB"},"content":{"rendered":"\n<p>En 2023, OLIMEX sortait une carte de d\u00e9veloppement \u00e0 base de FPGA GateMate (CologneChip):<\/p>\n\n\n\n<p><a href=\"https:\/\/www.digikey.com\/en\/products\/detail\/olimex-ltd\/GATEMATEA1-EVB\/22258042\">La GateMateA1-EVB<\/a> est une carte bien moins cher que le kit de d\u00e9veloppement officiel et propose tout un tas d&rsquo;interfaces int\u00e9ressantes.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><a href=\"https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/gatematea1_carte.jpg\"><img loading=\"lazy\" decoding=\"async\" width=\"600\" height=\"374\" src=\"https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/gatematea1_carte.jpg\" alt=\"\" class=\"wp-image-2427\" srcset=\"https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/gatematea1_carte.jpg 600w, https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/gatematea1_carte-300x187.jpg 300w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/a><figcaption class=\"wp-element-caption\">Vue de la carte GateMateA1-EVB<\/figcaption><\/figure>\n\n\n\n<p>Elle \u00e9tait dans mes cartons depuis un certain temps et je n&rsquo;avais pas encore pris le temps de la tester.<\/p>\n\n\n\n<p>Le site officiel donne<a href=\"https:\/\/www.olimex.com\/Products\/FPGA\/GateMate\/GateMateA1-EVB\/open-source-hardware\"> la liste de caract\u00e9ristiques compl\u00e8te<\/a>s:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>CCGM1A1 FPGA with 20480 logic cells<\/li>\n\n\n\n<li>PSRAM 64Mbit<\/li>\n\n\n\n<li>RP2040 processor for programing and debugging<\/li>\n\n\n\n<li>2MB configuration Flash for RP2040<\/li>\n\n\n\n<li>4 buttons<\/li>\n\n\n\n<li>USB-C for power supply and programming<\/li>\n\n\n\n<li>PS2 connector<\/li>\n\n\n\n<li>VGA connector<\/li>\n\n\n\n<li>4 Banks with signals with selectable levels 1.2V 1.8V 2.5V<\/li>\n\n\n\n<li>PMOD with level shifters<\/li>\n\n\n\n<li>UEXT with level shifters<\/li>\n\n\n\n<li>Power LED<\/li>\n\n\n\n<li>User LED<\/li>\n\n\n\n<li>4 sections configuration slide switch<\/li>\n\n\n\n<li>Dimensions: 120 x 80 mm<\/li>\n<\/ul>\n\n\n\n<p>Et le pilotage (communication, programmation alimentation debug) se fait via un connecteur USB-C connect\u00e9 sur un microcontr\u00f4leur <a href=\"https:\/\/www.raspberrypi.com\/products\/rp2040\/\">RP2040<\/a>.<\/p>\n\n\n\n<p>La plupart des signaux qui sortent sur les connecteurs sont branch\u00e9s directement sur les bank du FPGA. Ils sont donc \u00e0 la tension du bank : 1v2, 1v8 ou 2v5. Se sont des tensions assez faible dans les montages. Si l&rsquo;on veut du 3v3 il faudra se rabattre sur les connecteurs <a href=\"https:\/\/en.wikipedia.org\/wiki\/UEXT\">Uext1<\/a> et <a href=\"https:\/\/digilent.com\/blog\/where-to-plug-in-your-pmod-fpga\/\">Pmod1<\/a> qui poss\u00e8dent des transformateurs de niveaux de tension bidirectionnels.<\/p>\n\n\n\n<p>Les fichiers de d\u00e9veloppement de la carte (Kicad) ainsi que le code source d&rsquo;exemple sont fournis sur un <a href=\"https:\/\/github.com\/OLIMEX\/GateMateA1-EVB\/\">d\u00e9pot git.<\/a><\/p>\n\n\n\n<p>Bref, une belle carte lib\u00e9r\u00e9e en perspective.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Mise en route<\/h2>\n\n\n\n<p>Sous Linux, au branchement de l&rsquo;usb le message noyau suivant s&rsquo;affiche:<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>&#91;fabien:~\/projets] $ sudo dmesg -ce\n&#91;janv.17 20:57] usb 1-1.3.3: new full-speed USB device number 38 using ehci-pci\n&#91;  +0,111290] usb 1-1.3.3: New USB device found, idVendor=1209, idProduct=c0ca, bcdDevice= 1.10\n&#91;  +0,000005] usb 1-1.3.3: New USB device strings: Mfr=1, Product=2, SerialNumber=3\n&#91;  +0,000002] usb 1-1.3.3: Product: DirtyJTAG\n&#91;  +0,000001] usb 1-1.3.3: Manufacturer: Jean THOMAS\n&#91;  +0,000001] usb 1-1.3.3: SerialNumber: 2600942311111956\n&#91;  +0,018771] cdc_acm 1-1.3.3:1.1: ttyACM0: USB ACM device\n&#91;  +0,000018] usbcore: registered new interface driver cdc_acm\n&#91;  +0,000002] cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters\n<\/code><\/pre>\n\n\n\n<p>Nous voyons que le RP2040 nous expose un firmware DirtyJTAG ainsi qu&rsquo;une UART ttyACM0.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Exemple : un analyseur logique<\/h2>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><a href=\"https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/gatemate_ila_sch_screen.png\"><img loading=\"lazy\" decoding=\"async\" width=\"607\" height=\"510\" src=\"https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/gatemate_ila_sch_screen.png\" alt=\"\" class=\"wp-image-2430\" srcset=\"https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/gatemate_ila_sch_screen.png 607w, https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/gatemate_ila_sch_screen-300x252.png 300w\" sizes=\"auto, (max-width: 607px) 100vw, 607px\" \/><\/a><\/figure><\/div>\n\n\n<p>L&rsquo;exemple qui est donn\u00e9 dans le manuel de r\u00e9f\u00e9rence de la carte est un analyseur logique open source d\u00e9velopp\u00e9 par CologneChip : <a href=\"https:\/\/github.com\/colognechip\/gatemate_ila\">Gatemate ILA<\/a> (Integrated Logic Analyser).<\/p>\n\n\n\n<p>On va commencer par installer gatemate ILA :<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>cd \/opt\/gatemate\/\ngit clone https:\/\/github.com\/colognechip\/gatemate_ila.git\ncd gatemate_ila\/app\npython3 -m pip install -r requirements.txt <\/code><\/pre>\n\n\n\n<p>Il faut bien sur installer \u00e9galement la cha\u00eene de d\u00e9veloppement de <a href=\"http:\/\/python3 -m ensurepip --upgrade\">cologne chip<\/a>. Et modifier le fichier app\/config.py pour y inscrir les paths complet des utilitaires suivants:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>yosys<\/li>\n\n\n\n<li>p_r<\/li>\n\n\n\n<li>openFPGALoader<\/li>\n\n\n\n<li>gtkwave<\/li>\n<\/ul>\n\n\n\n<p>S&rsquo;ils ne se trouvent pas dans le path g\u00e9n\u00e9ral du projet. Pour ma part il n&rsquo;y a que p_r qui est sp\u00e9cifique au gatemate et que je n&rsquo;ai pas install\u00e9 globalement. J&rsquo;ai donc t\u00e9l\u00e9charg\u00e9 le kit de dev sur le site de <a href=\"https:\/\/colognechip.com\/programmable-logic\/gatemate\/gatemate-download\/\">colognechip<\/a> (10.01.2025) et modifi\u00e9 la ligne suivante dans app\/config.py<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>PR = '\/opt\/gatemate\/cc-toolchain-linux\/bin\/p_r\/p_r'<\/code><\/pre>\n\n\n\n<p>Les modes de programmation du gatemate avec openFPGALoader sont donn\u00e9s <a href=\"https:\/\/trabucayre.github.io\/openFPGALoader\/vendors\/colognechip.html\">dans la doc<\/a>.<\/p>\n\n\n\n<p>Dans le m\u00eame fichier, on modifie \u00e9galement les flags pour utiliser la sonde DirtyJTAG flash\u00e9e dans le RP2040 :<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>UPLOAD_FLAGS = ' -b olimex_gatemateevb '        \nCON_DEVICE = 'oli' # O.L.I. France inter, je suis pas petit ...<\/code><\/pre>\n\n\n\n<p>Dans un premier temps on va rester sur le bug du firmware qui oblige \u00e0 appuyer sur le bouton reset \u00e0 chaque fois qu&rsquo;on configure le FPGA.<\/p>\n\n\n\n<p>Le script qui contr\u00f4le l&rsquo;ILA se nomme ILAcop pour ILA COntrol Program:<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>python3 ILAcop.py --help\nusage: ILAcop.py &#91;-h] &#91;--version] &#91;--clean] &#91;--showdev] &#91;-wd WORK_DIR] {config,start,reconfig} ...\n\nGateMate ILA control program. With this script, you can configure and execute the ILA with a design under test (DUT).\n\noptions:\n  -h, --help            show this help message and exit\n  --version             show program's version number and exit\n  --clean               Deletes all output files created by the program.\n  --showdev             Outputs all found FTDI ports.\n  -wd WORK_DIR          Folder from which Yosys should be started for the synthesis of the Design Under Test.\n\nmain_actions:\n  {config,start,reconfig}\n\nexample usage:\npython3 ILAcop.py &#91;Commands]\n\nCommands:\n  config:   Configure the ILA.\n             -vlog SOURCE    Paths to the Verilog source code files.\n             -vhd SOURCE     Paths to the VHDL source code files.\n             -t NAME         Top level entity of the design under test.\n             -ccf SOURCE     Folder containing the .ccf file of the design under test. \n             -s SPEED        Configure ILA for best performance. Max Sample Width = 40, the number of samples depends on the sample width. \n             -f MHz          Defines the external clock frequency in MHz (default is 10.0 MHz).\n             -sync LEVEL     Number of register levels via which the SUT are synchronised (default: 2)\n             -d DELAY        ILA PLL Phase shift of sampling frequency. 0=0\u00b0, 1=90\u00b0, 2=180\u00b0, 3=270\u00b0 (default: 2).\n             -opt            Optimizes the design by deleting all unused signals before design evaluation.\n          (optional) Subcommands config: \n                -create_json: Creates a JSON file in which the logic analyzer can be configured.\n            NOTE: Without the subcommand the configurations are requested step by step via the terminal.\n  \n  reconfig: Configures the ILA based on a JSON file. With this option you have to specify a JSON file with -l &#91;filename].json.\n  \n  start     Starts the communication to the ILA with the last uploaded config\n    -s  The -s parameter prevents the FPGA from being reconfigured on restart.<\/code><\/pre>\n\n\n\n<p>Pour configurer le FPGA il semble devoir lancer la commande suivante (dans app\/):<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>$ python3 ILAcop.py config -vlog ..\/example_dut\/blink\/src\/ -t blink\n\n#################################################################################################\n#                   Cologne Chip GateMate ILA control program (ILAcop)                          #\n# ********************************************************************************************* #\n#    Copyright (C) 2023 Cologne Chip AG &lt;support@colognechip.com&gt;                               #\n#    Developed by Dave Fohrn                                                                    #\n#                                                                                               #\n#    This program is free software: you can redistribute it and\/or modify                       #\n#    it under the terms of the GNU General Public License as published by                       #\n#    the Free Software Foundation, either version 3 of the License, or                          #\n#    (at your option) any later version.                                                        #\n#                                                                                               #\n#    This program is distributed in the hope that it will be useful,                            #\n#    but WITHOUT ANY WARRANTY; without even the implied warranty of                             #\n#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the                              #\n#    GNU General Public License for more details.                                               #\n#                                                                                               #\n#    You should have received a copy of the GNU General Public License                          #\n#    along with this program.  If not, see &lt;https:\/\/www.gnu.org\/licenses\/&gt;.                     #\n#                                                                                               #\n# ********************************************************************************************* #\n#################################################################################################\n\n\n################# ccf File ##################\n#                                           #\n# blink.ccf                                 #\n#                                           #\n#############################################\n\n\n############### verilog Files ###############\n#                                           #\n# blink.v                                   #\n#                                           #\n#############################################\n\nExamine DUT ...\n\nAn error has occurred:\nERROR: Module `\\CC_USR_RSTN' referenced in module `\\blink' in cell `\\usr_rstn_inst' is not part of the design.\n\nyosys cmd: \nyosys -l \/opt\/gatemate\/gatemate_ila\/log\/yosys_DUT.log -p \" read -sv \/opt\/gatemate\/gatemate_ila\/example_dut\/blink\/src\/blink.v; read_verilog -lib -specify +\/gatemate\/cells_sim.v +\/gatemate\/cells_bb.v; hierarchy -check -top blink; proc; flatten; tribuf -logic; deminout; write_verilog \/opt\/gatemate\/gatemate_ila\/app\/config_design\/blink_25-01-17_22-08-52_flat.v ; check;  alumacc; opt; memory -nomap; opt_clean; memory_libmap -lib +\/gatemate\/brams.txt; techmap -map +\/gatemate\/brams_map.v;  stat -width\"\n<\/code><\/pre>\n\n\n\n<p>Mais pour le moment \u00e7a ne marche pas. Un mysterieux module CC_USR_RSTN n&rsquo;est pas r\u00e9f\u00e9renc\u00e9.<\/p>\n\n\n\n<p>Si on essais l&rsquo;exemple en VHDL c&rsquo;est pas beaucoup mieux, m\u00eame si l&rsquo;erreur est diff\u00e9rente (pourtant j&rsquo;ai bien ghdl install\u00e9 sur ma machine):<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>$ python3 ILAcop.py config -vhd ..\/example_dut\/blink\/src\/ -t blink\n\n#################################################################################################\n#                   Cologne Chip GateMate ILA control program (ILAcop)                          #\n# ********************************************************************************************* #\n#    Copyright (C) 2023 Cologne Chip AG &lt;support@colognechip.com&gt;                               #\n#    Developed by Dave Fohrn                                                                    #\n#                                                                                               #\n#    This program is free software: you can redistribute it and\/or modify                       #\n#    it under the terms of the GNU General Public License as published by                       #\n#    the Free Software Foundation, either version 3 of the License, or                          #\n#    (at your option) any later version.                                                        #\n#                                                                                               #\n#    This program is distributed in the hope that it will be useful,                            #\n#    but WITHOUT ANY WARRANTY; without even the implied warranty of                             #\n#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the                              #\n#    GNU General Public License for more details.                                               #\n#                                                                                               #\n#    You should have received a copy of the GNU General Public License                          #\n#    along with this program.  If not, see &lt;https:\/\/www.gnu.org\/licenses\/&gt;.                     #\n#                                                                                               #\n# ********************************************************************************************* #\n#################################################################################################\n\n\n################# ccf File ##################\n#                                           #\n# blink.ccf                                 #\n#                                           #\n#############################################\n\n\n################ vhdl Files #################\n#                                           #\n# blink.vhd                                 #\n#                                           #\n#############################################\n\nExamine DUT ...\n\nAn error has occurred:\nERROR: No such command: ghdl (type 'help' for a command overview)\n\nyosys cmd: \nyosys -l \/opt\/gatemate\/gatemate_ila\/log\/yosys_DUT.log -p \" ghdl --warn-no-binding -C --ieee=synopsys \/opt\/gatemate\/gatemate_ila\/example_dut\/blink\/src\/blink.vhd  -e blink; hierarchy -check -top blink; proc; flatten; tribuf -logic; deminout; write_verilog \/opt\/gatemate\/gatemate_ila\/app\/config_design\/blink_25-01-17_22-12-24_flat.v ; check;  alumacc; opt; memory -nomap; opt_clean; memory_libmap -lib +\/gatemate\/brams.txt; techmap -map +\/gatemate\/brams_map.v;  stat -width\"\n<\/code><\/pre>\n\n\n\n<p>Dans le cas de verilog, le probl\u00e8me vient de la version de yosys utilis\u00e9. Si on modifie le fichier config.py pour pointer vers le yosys fourni par CologneChip \u00e7a fonctionne :<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>YOSYS = '\/opt\/gatemate\/cc-toolchain-linux\/bin\/yosys\/yosys'<\/code><\/pre>\n\n\n\n<p>On peut lancer la commande :<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>$ python3 ILAcop.py config -vlog ..\/example_dut\/blink\/src\/ -t blink\n\n#################################################################################################\n#                   Cologne Chip GateMate ILA control program (ILAcop)                          #\n# ********************************************************************************************* #\n#    Copyright (C) 2023 Cologne Chip AG &lt;support@colognechip.com>                               #\n#    Developed by Dave Fohrn                                                                    #\n#                                                                                               #\n#    This program is free software: you can redistribute it and\/or modify                       #\n#    it under the terms of the GNU General Public License as published by                       #\n#    the Free Software Foundation, either version 3 of the License, or                          #\n#    (at your option) any later version.                                                        #\n#                                                                                               #\n#    This program is distributed in the hope that it will be useful,                            #\n#    but WITHOUT ANY WARRANTY; without even the implied warranty of                             #\n#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the                              #\n#    GNU General Public License for more details.                                               #\n#                                                                                               #\n#    You should have received a copy of the GNU General Public License                          #\n#    along with this program.  If not, see &lt;https:\/\/www.gnu.org\/licenses\/>.                     #\n#                                                                                               #\n# ********************************************************************************************* #\n#################################################################################################\n\n\n################# ccf File ##################\n#                                           #\n# blink.ccf                                 #\n#                                           #\n#############################################\n\n\n############### verilog Files ###############\n#                                           #\n# blink.v                                   #\n#                                           #\n#############################################\n\nExamine DUT ...\n\n\n############# Block RAM in use ##############\n#                                           #\n# CC_BRAM_20K in use: 0                     #\n# CC_BRAM_40K in use: 0                     #\n#                                           #\n#############################################\n\n\n############ Found PLL instance #############\n#                                           #\n# Pll name  = pll_inst                      #\n# Frequency = 25 MHz                        #\n#                                           #\n#############################################\n\n########### Found CC_USR_RSTN ###########\n\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!! NOTE !!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n!                                                              !\n! Now you will be guided through the configuration of the ILA. !\n! Entering 'e' exits the process and generates a configurable  !\n! JSON file for the given DUT.                                 !\n! Enter 'p' for 'previous' to backtrack a step.                !\n!                                                              !\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! NOTE !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n!                                                                       !\n! In the following, a clock source for the ILA should be selected.      !\n! Usually, the same clk signal that clocks the tested signals suffices. !\n!                                                                       !\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\nHere are the possible ways to provide a clock to the ILA:\n\n 1 = Use an external clk input signal.\n 2 = Use an additional PLL with a freely selectable frequency (additional net of the global Mesh are required).\n 3 = Use a signal generated by a PLL from your design.\n\nPlease choose between 1 and 3: 3\n\n########### PLL instances signals ###########\n#                                           #\n# pll_inst : 25 Mhz                         #\n#                                           #\n#  0 = CLK0                                 #\n#  1 = CLK180                               #\n#  2 = CLK270                               #\n#  3 = CLK90                                #\n#                                           #\n#                                           #\n#############################################\n\n\nAttention! If you choose an output signal of a PLL that you will not use in your design, an additional net of Global Mesh is required! \n\nChoose a clock signal: 0\n\n!!!!!!!!!!!!!!!!!!!!! User controllable reset !!!!!!!!!!!!!!!!!!!!!\n!                                                                 !\n! The ILA can hold the DUT in reset until capture starts.         !\n! This makes it possible to capture the start process of the DUT. !\n! Attention, the ila treats the signal as active LOW.             !\n!                                                                 !\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\nThe following options are available:\n\n 1 = Use an external reset input signal.\n 2 = Deactivate this function.\n 3 = Use the ouput signal from the CC_USR_RSTN primitive in your design. (The functionality of the CC_USR_RSTN primitive is still given).\n\nPlease choose between 1 and 3: 2\n\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! NOTE !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n!                                                                                                 !\n! You will be prompted to select signals for analysis from those found in your design under test. !\n!                                                                                                 !\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\n------------------------- blink --------------------------\n+----+-------------------+--------+----------+-----------+\n|  # | name              | range  | selected | hierarchy |\n+----+-------------------+--------+----------+-----------+\n|  1 | LED_ctrl          |   1    |    &#91;]    |           |\n|  2 | clk               |   1    |    &#91;]    |           |\n|  3 | clk0              |   1    |    &#91;]    |           |\n|  4 | clk180            |   1    |    &#91;]    |           |\n|  5 | clk270            |   1    |    &#91;]    |           |\n|  6 | clk90             |   1    |    &#91;]    |           |\n|  7 | counter           | &#91;24:0] |    &#91;]    |           |\n|  8 | led               | &#91;7:0]  |    &#91;]    |           |\n|  9 | rst               |   1    |    &#91;]    |           |\n| 10 | usr_pll_lock      |   1    |    &#91;]    |           |\n| 11 | usr_pll_lock_stdy |   1    |    &#91;]    |           |\n| 12 | usr_ref_out       |   1    |    &#91;]    |           |\n+----+-------------------+--------+----------+-----------+\n\n## Number of selected bits to be analysed ###\n#                                           #\n# 0 (max. 2400)                             #\n#                                           #\n#############################################\n\nSelect signals to be analyzed (0 = finish): 7\n\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! NOTE !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n!                                                                                  !\n! Define a range for the vector to be analyzed.                                    !\n!  you can do this in the following ways:                                          !\n!   1) Press enter to analyze the entire vector                                    !\n!   2) Define an area of the vector. (The area should be within the vector area):  !\n!        e.g.: '&#91;1:0]'                                                             !\n!   3) Individual signals:                                                         !\n!        e.g.: '1'                                                                 !\n!   4) Any combination of areas and individual signals                             !\n!        e.g.: '9, &#91;7:5], 3, &#91;1:0]'                                                !\n! define Signals in descending order!                                              !\n!                                                                                  !\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\nreg &#91;24:0] counter: \n\n\n------------------------- blink --------------------------\n+----+-------------------+--------+----------+-----------+\n|  # | name              | range  | selected | hierarchy |\n+----+-------------------+--------+----------+-----------+\n|  1 | LED_ctrl          |   1    |    &#91;]    |           |\n|  2 | clk               |   1    |    &#91;]    |           |\n|  3 | clk0              |   1    |    &#91;]    |           |\n|  4 | clk180            |   1    |    &#91;]    |           |\n|  5 | clk270            |   1    |    &#91;]    |           |\n|  6 | clk90             |   1    |    &#91;]    |           |\n|  7 | counter           | &#91;24:0] |  &#91;'A']   |           |\n|  8 | led               | &#91;7:0]  |    &#91;]    |           |\n|  9 | rst               |   1    |    &#91;]    |           |\n| 10 | usr_pll_lock      |   1    |    &#91;]    |           |\n| 11 | usr_pll_lock_stdy |   1    |    &#91;]    |           |\n| 12 | usr_ref_out       |   1    |    &#91;]    |           |\n+----+-------------------+--------+----------+-----------+\n\n## Number of selected bits to be analysed ###\n#                                           #\n# 25 (max. 2400)                            #\n#                                           #\n#############################################\n\nSelect signals to be analyzed (0 = finish): 1\n\n------------------------- blink --------------------------\n+----+-------------------+--------+----------+-----------+\n|  # | name              | range  | selected | hierarchy |\n+----+-------------------+--------+----------+-----------+\n|  1 | LED_ctrl          |   1    |  &#91;'A']   |           |\n|  2 | clk               |   1    |    &#91;]    |           |\n|  3 | clk0              |   1    |    &#91;]    |           |\n|  4 | clk180            |   1    |    &#91;]    |           |\n|  5 | clk270            |   1    |    &#91;]    |           |\n|  6 | clk90             |   1    |    &#91;]    |           |\n|  7 | counter           | &#91;24:0] |  &#91;'A']   |           |\n|  8 | led               | &#91;7:0]  |    &#91;]    |           |\n|  9 | rst               |   1    |    &#91;]    |           |\n| 10 | usr_pll_lock      |   1    |    &#91;]    |           |\n| 11 | usr_pll_lock_stdy |   1    |    &#91;]    |           |\n| 12 | usr_ref_out       |   1    |    &#91;]    |           |\n+----+-------------------+--------+----------+-----------+\n\n## Number of selected bits to be analysed ###\n#                                           #\n# 26 (max. 2400)                            #\n#                                           #\n#############################################\n\nSelect signals to be analyzed (0 = finish): 8\n\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! NOTE !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n!                                                                                  !\n! Define a range for the vector to be analyzed.                                    !\n!  you can do this in the following ways:                                          !\n!   1) Press enter to analyze the entire vector                                    !\n!   2) Define an area of the vector. (The area should be within the vector area):  !\n!        e.g.: '&#91;1:0]'                                                             !\n!   3) Individual signals:                                                         !\n!        e.g.: '1'                                                                 !\n!   4) Any combination of areas and individual signals                             !\n!        e.g.: '9, &#91;7:5], 3, &#91;1:0]'                                                !\n! define Signals in descending order!                                              !\n!                                                                                  !\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\nwire &#91;7:0] led: \n\n\n------------------------- blink --------------------------\n+----+-------------------+--------+----------+-----------+\n|  # | name              | range  | selected | hierarchy |\n+----+-------------------+--------+----------+-----------+\n|  1 | LED_ctrl          |   1    |  &#91;'A']   |           |\n|  2 | clk               |   1    |    &#91;]    |           |\n|  3 | clk0              |   1    |    &#91;]    |           |\n|  4 | clk180            |   1    |    &#91;]    |           |\n|  5 | clk270            |   1    |    &#91;]    |           |\n|  6 | clk90             |   1    |    &#91;]    |           |\n|  7 | counter           | &#91;24:0] |  &#91;'A']   |           |\n|  8 | led               | &#91;7:0]  |  &#91;'A']   |           |\n|  9 | rst               |   1    |    &#91;]    |           |\n| 10 | usr_pll_lock      |   1    |    &#91;]    |           |\n| 11 | usr_pll_lock_stdy |   1    |    &#91;]    |           |\n| 12 | usr_ref_out       |   1    |    &#91;]    |           |\n+----+-------------------+--------+----------+-----------+\n\n## Number of selected bits to be analysed ###\n#                                           #\n# 34 (max. 2400)                            #\n#                                           #\n#############################################\n\nSelect signals to be analyzed (0 = finish): 0\n\n!!!!!!!!!!!!!!!!!!! Note !!!!!!!!!!!!!!!!!!!!\n!                                           !\n! The capture duration must be defined.     !\n! The maximum duration depends on:          !\n!  - available ram                          !\n!  - width of the sample                    !\n!  - sampling frequency                     !\n! FIFO Cascade (Width x Depth)              !\n! FIFO (Input Width x Depth)                !\n!                                           !\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n------Please choose one of the following durations: -------\n+----+---------+---------------+--------------+-----------+\n|  # | smp_cnt | duration &#91;us] | FIFO Cascade |      FIFO |\n+----+---------+---------------+--------------+-----------+\n|  1 |    1024 |         40.96 |        1 x 1 | 40 x 1024 |\n|  2 |    2048 |         81.92 |        1 x 2 | 40 x 1024 |\n|  3 |    3072 |        122.88 |        1 x 3 | 40 x 1024 |\n|  4 |    4096 |        163.84 |        4 x 1 | 10 x 4096 |\n|  5 |    5120 |         204.8 |        1 x 5 | 40 x 1024 |\n|  6 |    6144 |        245.76 |        1 x 6 | 40 x 1024 |\n|  7 |    8192 |        327.68 |        4 x 2 | 10 x 4096 |\n|  8 |   12288 |        491.52 |        4 x 3 | 10 x 4096 |\n|  9 |   16384 |        655.36 |        4 x 4 | 10 x 4096 |\n| 10 |   20480 |         819.2 |        4 x 5 | 10 x 4096 |\n| 11 |   24576 |        983.04 |        4 x 6 | 10 x 4096 |\n+----+---------+---------------+--------------+-----------+\n\nTotal Capture duration (choose between 1 and 11): 1\n\n############# Capture duration ##############\n#                                           #\n# Sample count = 1024                       #\n# Capture duration = 40.96 us               #\n#                                           #\n#############################################\n\n\nEnter the number of capture samples before trigger activation (between 0 and 250): 10\n\n###### Capture duration before Trigger ######\n#                                           #\n# Sample count = 10                         #\n# Capture duration = 0.52 us                #\n#                                           #\n#############################################\n\n\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! Note !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n!                                                                                   !\n! You can override an input or input-vector of your top-level entity using the ILA. !\n! Please note that the input will no longer be connected to the FPGA's IO pins.     !\n!                                                                                   !\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\nWould you like to implement the input control feature? (y\/N): \n\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! Note !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n!                                                                         !\n! There are two default triggers that can be set for exactly one signal:  !\n!  'rising edge' and 'falling edge'                                       !\n! There is also an optional trigger: pattern compare                      !\n! With this option, a pattern can be set across the entire bit width,     !\n!  determining for each bit whether it should be '1', '0', or 'dc'        !\n!  (don't care) to activate the trigger.                                  !\n! If this function is activated, more hardware is required for the ILA    !\n!  and the maximum possible sampling frequency may be reduced.            !\n!                                                                         !\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\nWould you like to implement the function for comparing bit patterns? (y\/N): \n\n############ Signals under test #############\n#                                           #\n# LED_ctrl                                  #\n# &#91;24:0] counter                            #\n# &#91;7:0] led                                 #\n#                                           #\n#############################################\n\nExecute Synthesis...\nOutput permanently saved to: \/opt\/gatemate\/gatemate_ila\/log\/yosys.log\n\nExecute Implementation...\nOutput permanently saved to: \/opt\/gatemate\/gatemate_ila\/log\/impl.log\n\n################# Configuration File ##################\n#                                                     #\n# save_config\/ila_config_blink_25-01-18_07-19-48.json #\n#                                                     #\n#######################################################\n\nError configuring the device\nTraceback (most recent call last):\n  File \"\/opt\/gatemate\/gatemate_ila\/app\/ILAConfig.py\", line 1721, in upload\n    dev.set_configuration()\n  File \"\/usr\/lib\/python3\/dist-packages\/usb\/core.py\", line 915, in set_configuration\n    self._ctx.managed_set_configuration(self, configuration)\n  File \"\/usr\/lib\/python3\/dist-packages\/usb\/core.py\", line 113, in wrapper\n    return f(self, *args, **kwargs)\n  File \"\/usr\/lib\/python3\/dist-packages\/usb\/core.py\", line 158, in managed_set_configuration\n    self.managed_open()\n  File \"\/usr\/lib\/python3\/dist-packages\/usb\/core.py\", line 113, in wrapper\n    return f(self, *args, **kwargs)\n  File \"\/usr\/lib\/python3\/dist-packages\/usb\/core.py\", line 131, in managed_open\n    self.handle = self.backend.open_device(self.dev)\n  File \"\/usr\/lib\/python3\/dist-packages\/usb\/backend\/libusb1.py\", line 804, in open_device\n    return _DeviceHandle(dev)\n  File \"\/usr\/lib\/python3\/dist-packages\/usb\/backend\/libusb1.py\", line 652, in __init__\n    _check(_lib.libusb_open(self.devid, byref(self.handle)))\n  File \"\/usr\/lib\/python3\/dist-packages\/usb\/backend\/libusb1.py\", line 604, in _check\n    raise USBError(_strerror(ret), ret, _libusb_errno&#91;ret])\nusb.core.USBError: &#91;Errno 13] Access denied (insufficient permissions)\n\nDuring handling of the above exception, another exception occurred:\n\nTraceback (most recent call last):\n  File \"\/opt\/gatemate\/gatemate_ila\/app\/ILAcop.py\", line 277, in &lt;module>\n    if not ILA_config_instance.upload():\n  File \"\/opt\/gatemate\/gatemate_ila\/app\/ILAConfig.py\", line 1726, in upload\n    if dev.is_kernel_driver_active(intf.bInterfaceNumber):\n  File \"\/usr\/lib\/python3\/dist-packages\/usb\/core.py\", line 1107, in is_kernel_driver_active\n    self._ctx.managed_open()\n  File \"\/usr\/lib\/python3\/dist-packages\/usb\/core.py\", line 113, in wrapper\n    return f(self, *args, **kwargs)\n  File \"\/usr\/lib\/python3\/dist-packages\/usb\/core.py\", line 131, in managed_open\n    self.handle = self.backend.open_device(self.dev)\n  File \"\/usr\/lib\/python3\/dist-packages\/usb\/backend\/libusb1.py\", line 804, in open_device\n    return _DeviceHandle(dev)\n  File \"\/usr\/lib\/python3\/dist-packages\/usb\/backend\/libusb1.py\", line 652, in __init__\n    _check(_lib.libusb_open(self.devid, byref(self.handle)))\n  File \"\/usr\/lib\/python3\/dist-packages\/usb\/backend\/libusb1.py\", line 604, in _check\n    raise USBError(_strerror(ret), ret, _libusb_errno&#91;ret])\nusb.core.USBError: &#91;Errno 13] Access denied (insufficient permissions)\n<\/code><\/pre>\n\n\n\n<p>Il semble que je n&rsquo;ai pas configur\u00e9 correctement l&rsquo;usb. Il faut ajouter une r\u00e8gle udev pour le DirtyJtag :<\/p>\n\n\n\n<p><\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>$ lsusb\n...\nBus 001 Device 043: ID 1209:c0ca Generic Jean THOMAS DirtyJTAG\n...<\/code><\/pre>\n\n\n\n<p>On ouvre ajoute un fichier de r\u00e8gle :<\/p>\n\n\n\n<p>sudo vim \/etc\/udev\/rules.d\/99-usb-serial.rules<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>SUBSYSTEM==\"usb\", ATTRS{idVendor}==\"1209\", ATTRS{idProduct}==\"c0ca\", MODE=\"0666\"\n<\/code><\/pre>\n\n\n\n<p>Puis on recharge udev:<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>sudo udevadm control --reload-rules\nsudo udevadm trigger<\/code><\/pre>\n\n\n\n<p>Le c\u00e2ble est maintenant accessible sans \u00eatre en sudo :<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>openFPGALoader --cable dirtyJtag --detect\nJtag frequency : requested 6000000Hz -> real 6000000Hz\nindex 0:\n\tidcode 0x20000001\n\tmanufacturer colognechip\n\tfamily GateMate Series\n\tmodel  GM1Ax\n\tirlength 6<\/code><\/pre>\n\n\n\n<p>On va plus loin cette fois, mais il ne trouve pas la carte :<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>...\n################# Configuration File ##################\n#                                                     #\n# save_config\/ila_config_blink_25-01-18_07-47-38.json #\n#                                                     #\n#######################################################\n\n\nUpload to FPGA Board...\nExecute openFPGALoader command:\nopenFPGALoader  -b olimex_gatemateevb \/opt\/gatemate\/gatemate_ila\/p_r_out\/ila_top_25-01-18_07-47-38_00.cfg\n\n\nError: \n\nError: cannot find board 'olimex_gatemateevb'<\/code><\/pre>\n\n\n\n<p>Il semble que ma version d&rsquo;openFPGALoader soit trop vieille, et une sombre histoire de libstdc++ m&#8217;emp\u00eache d&rsquo;utiliser correctement le binaire fourni par CologneChip.<\/p>\n\n\n\n<p>Mettons donc \u00e0 jour les sources officielles:<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>$ cd \/opt\/openFPGALoader\n$ git pull -r\n$ rm -rf build\n$ mkdir build\n$ cd build\/\n$ cmake ..\n$ cmake --build .\n$ make -j10\n$ sudo make install<\/code><\/pre>\n\n\n\n<p>Cette fois le fichier de dump vcd est cr\u00e9\u00e9 et une fen\u00eate gtkwave s&rsquo;ouvre sur les chronogrammes saisis !<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>$ python3 ILAcop.py start\n\n#################################################################################################\n#                   Cologne Chip GateMate ILA control program (ILAcop)                          #\n# ********************************************************************************************* #\n#    Copyright (C) 2023 Cologne Chip AG &lt;support@colognechip.com>                               #\n#    Developed by Dave Fohrn                                                                    #\n#                                                                                               #\n#    This program is free software: you can redistribute it and\/or modify                       #\n#    it under the terms of the GNU General Public License as published by                       #\n#    the Free Software Foundation, either version 3 of the License, or                          #\n#    (at your option) any later version.                                                        #\n#                                                                                               #\n#    This program is distributed in the hope that it will be useful,                            #\n#    but WITHOUT ANY WARRANTY; without even the implied warranty of                             #\n#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the                              #\n#    GNU General Public License for more details.                                               #\n#                                                                                               #\n#    You should have received a copy of the GNU General Public License                          #\n#    along with this program.  If not, see &lt;https:\/\/www.gnu.org\/licenses\/>.                     #\n#                                                                                               #\n# ********************************************************************************************* #\n#################################################################################################\n\n\nUpload to FPGA Board...\nwriteTDI: read: usb bulk read failed &#91;Errno 110] Operation timed out\n\n############ CONFIGURATION NOTE #############\n#                                           #\n# Trigger at sample no.: 10                 #\n# Defined analysis frequency: 25000000 Hz   #\n#                                           #\n#############################################\n\n\n--- All Signals ----\n+----+-------------+\n|  # |        Name |\n+----+-------------+\n|  0 |      led&#91;0] |\n|  1 |      led&#91;1] |\n|  2 |      led&#91;2] |\n|  3 |      led&#91;3] |\n|  4 |      led&#91;4] |\n|  5 |      led&#91;5] |\n|  6 |      led&#91;6] |\n|  7 |      led&#91;7] |\n|  8 |  counter&#91;0] |\n|  9 |  counter&#91;1] |\n| 10 |  counter&#91;2] |\n| 11 |  counter&#91;3] |\n| 12 |  counter&#91;4] |\n| 13 |  counter&#91;5] |\n| 14 |  counter&#91;6] |\n| 15 |  counter&#91;7] |\n| 16 |  counter&#91;8] |\n| 17 |  counter&#91;9] |\n| 18 | counter&#91;10] |\n| 19 | counter&#91;11] |\n| 20 | counter&#91;12] |\n| 21 | counter&#91;13] |\n| 22 | counter&#91;14] |\n| 23 | counter&#91;15] |\n| 24 | counter&#91;16] |\n| 25 | counter&#91;17] |\n| 26 | counter&#91;18] |\n| 27 | counter&#91;19] |\n| 28 | counter&#91;20] |\n| 29 | counter&#91;21] |\n| 30 | counter&#91;22] |\n| 31 | counter&#91;23] |\n| 32 | counter&#91;24] |\n| 33 |    LED_ctrl |\n+----+-------------+\n\n##### current ILA runtime configuration #####\n#                                           #\n# Number of sequences: 1                    #\n#                                           #\n#  Sequences Number: 1                      #\n#     trigger activation: falling edge      #\n#     trigger signal:     led&#91;0]            #\n#                                           #\n#############################################\n\n\n\n0 -- exit\n1 -- change Trigger\n2 -- start capture\n3 -- reset ILA (resets the config of the ILA)\n\nEnter your choice: 2\n\n################# start Capture #################\n#                                               #\n# Waiting for device. Press Enter to interrupt. #\n#                                               #\n#################################################\n\n\n############### Duration between captures ##############\n#                                                      #\n# Duration between start and first trigger: 0.009355 s #\n#                                                      #\n########################################################\n\n\n############### create vcd file ###############\n#                                             #\n# vcd_files\/ila_blink_25-01-18_20-54-13_0.vcd #\n#                                             #\n###############################################\n\n\nPress Enter to continue\n<\/code><\/pre>\n\n\n\n<figure class=\"wp-block-image size-full\"><a href=\"https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/gtkwave_ila_olimex_gatemate.png\"><img loading=\"lazy\" decoding=\"async\" width=\"904\" height=\"417\" src=\"https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/gtkwave_ila_olimex_gatemate.png\" alt=\"\" class=\"wp-image-2439\" srcset=\"https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/gtkwave_ila_olimex_gatemate.png 904w, https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/gtkwave_ila_olimex_gatemate-300x138.png 300w, https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/gtkwave_ila_olimex_gatemate-768x354.png 768w\" sizes=\"auto, (max-width: 904px) 100vw, 904px\" \/><\/a><\/figure>\n\n\n\n<p>Pas mal !<\/p>\n\n\n\n<p>Par contre plus aucune LED ne s&rsquo;allument hormis la rouge de l&rsquo;alimentation. Il est possible que le fichier de contraintes ne soit par correct. Le fichier se trouve dans le r\u00e9pertoire source de l&rsquo;exemple : <\/p>\n\n\n\n<p>Fichier \/opt\/gatemate\/gatemate_ila\/example_dut\/blink\/src\/blink.ccf:<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>Pin_in   \"clk\"  Loc = \"IO_SB_A8\" | SCHMITT_TRIGGER=true;\nPin_out  \"led&#91;0]\"                   Loc = \"IO_EB_B1\";                           # LED D1\nPin_out  \"led&#91;1]\"                   Loc = \"IO_EB_B2\";                           # LED D2\nPin_out  \"led&#91;2]\"                   Loc = \"IO_EB_B3\";                           # LED D1\nPin_out  \"led&#91;3]\"                   Loc = \"IO_EB_B4\";                           # LED D2\nPin_out  \"led&#91;4]\"                   Loc = \"IO_EB_B5\";                           # LED D1\nPin_out  \"led&#91;5]\"                   Loc = \"IO_EB_B6\";                           # LED D2\nPin_out  \"led&#91;6]\"                   Loc = \"IO_EB_B7\";                           # LED D1\nPin_out  \"led&#91;7]\"                   Loc = \"IO_EB_B8\";                           # LED D2\n<\/code><\/pre>\n\n\n\n<p>Si l&rsquo;on regarde la carte, les IO_EB_Bx se trouvent sur le bank BANK_EB1\u00a0qui ne sont pas connect\u00e9 \u00e0 des leds.<\/p>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><a href=\"https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/BANK_EB1.png\"><img loading=\"lazy\" decoding=\"async\" width=\"378\" height=\"213\" src=\"https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/BANK_EB1.png\" alt=\"\" class=\"wp-image-2440\" srcset=\"https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/BANK_EB1.png 378w, https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/BANK_EB1-300x169.png 300w\" sizes=\"auto, (max-width: 378px) 100vw, 378px\" \/><\/a><\/figure><\/div>\n\n\n<p><\/p>\n\n\n\n<p>Notez que pour ouvrir les sch\u00e9ma de la carte, kicad 6 ne suffit pas. Sur Linux Mint on peut installer kicad 8 avec les commandes suivante:<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>$  sudo add-apt-repository ppa:kicad\/kicad-8.0-releases\n$  sudo apt update\n$  sudo apt install kicad\n<\/code><\/pre>\n\n\n\n<p>La led sur le schema:<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><a href=\"https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/olimex_evb_gatemate_led_sch.png\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"430\" src=\"https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/olimex_evb_gatemate_led_sch-1024x430.png\" alt=\"\" class=\"wp-image-2442\" srcset=\"https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/olimex_evb_gatemate_led_sch-1024x430.png 1024w, https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/olimex_evb_gatemate_led_sch-300x126.png 300w, https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/olimex_evb_gatemate_led_sch-768x323.png 768w, https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/olimex_evb_gatemate_led_sch.png 1305w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/a><\/figure>\n\n\n\n<p>Se trouve sur le port <strong>IO_SB_B6<\/strong> du gatemate:<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><a href=\"https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/gatemate_io_sb_b6_fpga_led.png\"><img loading=\"lazy\" decoding=\"async\" width=\"930\" height=\"278\" src=\"https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/gatemate_io_sb_b6_fpga_led.png\" alt=\"\" class=\"wp-image-2443\" srcset=\"https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/gatemate_io_sb_b6_fpga_led.png 930w, https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/gatemate_io_sb_b6_fpga_led-300x90.png 300w, https:\/\/www.fabienm.eu\/flf\/wp-content\/uploads\/2025\/01\/gatemate_io_sb_b6_fpga_led-768x230.png 768w\" sizes=\"auto, (max-width: 930px) 100vw, 930px\" \/><\/a><\/figure>\n\n\n\n<p> Il faut donc en changer pour le pin de la LED FPGA_LED1 histoire d&rsquo;en voir au moins une clignoter.<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>Pin_in   \"clk\"  Loc = \"IO_SB_A8\" | SCHMITT_TRIGGER=true;\nPin_out  \"led&#91;0]\"                   Loc = \"IO_EB_B1\";                           # LED D1\nPin_out  \"led&#91;1]\"                   Loc = \"IO_EB_B2\";                           # LED D2\nPin_out  \"led&#91;2]\"                   Loc = \"IO_EB_B3\";                           # LED D1\nPin_out  \"led&#91;3]\"                   Loc = \"IO_EB_B4\";                           # LED D2\n#Pin_out  \"led&#91;4]\"                   Loc = \"IO_EB_B5\";                           # LED D1\nPin_out  \"led&#91;4]\"                   Loc = \"IO_SB_B6\";                           # FPGA_LED1 \nPin_out  \"led&#91;5]\"                   Loc = \"IO_EB_B6\";                           # LED D2\nPin_out  \"led&#91;6]\"                   Loc = \"IO_EB_B7\";                           # LED D1\nPin_out  \"led&#91;7]\"                   Loc = \"IO_EB_B8\";                           # LED D2 \n<\/code><\/pre>\n\n\n\n<p>On modifie le fichier ccf puis on clean le projet pour le relancer:<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>$ python3 ILAcop.py  --clean\n$ python3 ILAcop.py config -vlog ..\/example_dut\/blink\/src\/ -t blink\n$ python3 ILAcop.py start<\/code><\/pre>\n\n\n\n<p>Bon pour le coup j&rsquo;ai \u00e9t\u00e9 un peu vite et j&rsquo;ai du relancer toute la config. Mais on peut faire un clean sans avoir \u00e0 tout reconfigurer et relancer la derni\u00e8re configuration:<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>$ python3 ILAcop.py reconfig -l save_config\/ila_config_blink_25-01-18_21-31-30.json<\/code><\/pre>\n\n\n\n<p>Cette fois la LED verte du FPGA_LED1\u00a0clignote.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>It&rsquo;s blinking \\o\/<\/strong><\/h2>\n","protected":false},"excerpt":{"rendered":"<p>En 2023, OLIMEX sortait une carte de d\u00e9veloppement \u00e0 base de FPGA GateMate (CologneChip): La GateMateA1-EVB est une carte bien moins cher que le kit de d\u00e9veloppement officiel et propose tout un tas d&rsquo;interfaces int\u00e9ressantes. Elle \u00e9tait dans mes cartons depuis un certain temps et je n&rsquo;avais pas encore pris le temps de la tester. &hellip; <a href=\"https:\/\/www.fabienm.eu\/flf\/prise-en-main-de-la-gatematea1-evb\/\" class=\"more-link\">Continuer la lecture de <span class=\"screen-reader-text\">Prise en main de la GateMateA1-EVB<\/span> <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_uag_custom_page_level_css":"","footnotes":""},"categories":[22,24],"tags":[217,263,264],"class_list":["post-2426","post","type-post","status-publish","format-standard","hentry","category-blog","category-materiel","tag-gatemate","tag-gatematea1-evb","tag-rp2040"],"uagb_featured_image_src":{"full":false,"thumbnail":false,"medium":false,"medium_large":false,"large":false,"1536x1536":false,"2048x2048":false,"post-thumbnail":false},"uagb_author_info":{"display_name":"Fabien Marteau","author_link":"https:\/\/www.fabienm.eu\/flf\/author\/admin\/"},"uagb_comment_info":0,"uagb_excerpt":"En 2023, OLIMEX sortait une carte de d\u00e9veloppement \u00e0 base de FPGA GateMate (CologneChip): La GateMateA1-EVB est une carte bien moins cher que le kit de d\u00e9veloppement officiel et propose tout un tas d&rsquo;interfaces int\u00e9ressantes. Elle \u00e9tait dans mes cartons depuis un certain temps et je n&rsquo;avais pas encore pris le temps de la tester.\u2026","_links":{"self":[{"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/posts\/2426","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/comments?post=2426"}],"version-history":[{"count":11,"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/posts\/2426\/revisions"}],"predecessor-version":[{"id":2446,"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/posts\/2426\/revisions\/2446"}],"wp:attachment":[{"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/media?parent=2426"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/categories?post=2426"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.fabienm.eu\/flf\/wp-json\/wp\/v2\/tags?post=2426"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}